1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device having structural characteristics in the vicinity of lead frame for mounting a semiconductor chip or the like, and separately acting an electrical connecting function and a physical holding function between a semiconductor chip and a printed wiring substrate.
2. Description of the Related Art
In semiconductor chips as a center of a semiconductor device, it is demanded to satisfy the following requirements with respect to a gate array element mainly used in a microprocessor unit (MPU) or a semiconductor chip for OEM use (so-called custom IC). That is, there are demanded requirements of (1) reducing lead inductance for the control of switching noise; (2) efficiently dissipating heat generated due to the increase of power consumed with high speed operation; (3) fining an inner lead in accordance with the increase of input and output terminal number and the fineness of electrodes on the semiconductor element; (4) mounting multi-chips on a single printed wiring substrate for the enlargement of applicable functions; and so on.
In order to satisfy the above requirements, there are proposed various means having the following merits, i.e. (1) the lead inductance may be reduced by rendering the substrate into multi-layer structure; (2) the heat dissipation is surely improved by mounting a heat sink onto a rigid substrate; (3) the inner lead may be fined by utilizing a workability of the substrate; (4) the multi-chips may be mounted on the single substrate by increasing the degree of freedom in the design of the substrate; and so on. These means can effectively be applied to semiconductor devices each provided with an electronic component carrier formed, for example, by joining the substrate with the lead frame.
A first embodiment of the conventional semiconductor device as shown in Japanese Patent laid open No. 59-98545 is shown in FIG. 1. In this case, a given conductor pattern 2 is formed on an upper surface of a substrate 1 composed of a glass epoxy material and connected to a semiconductor chip 3 arranged on a proper position of the substrate 1 through an adhesive 7 with gold wires 4. Furthermore, the conductor pattern 2 is joined to a lead frame 5 for the connection to a given external element through soldering, while a through-hole 6 is formed in the substrate 1 at a position joined to the lead frame 5. Moreover, such an assembly is locally packaged with a mold resin 8 around the semiconductor chip 3.
A second embodiment of the conventional semiconductor device as shown in Japanese Patent laid open No. 59-98545 is shown in FIG. 2. In this case, a given conductor pattern 2 is formed on an upper surface of a substrate 1 composed of a glass epoxy material and connected to a semiconductor chip 3 mounted on a proper place of the substrate 1 with gold wires 4. Furthermore, the conductor pattern 2 is joined to a lead frame 5 for the connection to a given external element through soldering 9. Such an assembly is packaged with a mold resin 8 as a whole.
In the above conventional technique, however, there are the following problems.
[1] Both of electrical connecting function and physical holding function are generally included in the joint portion between the lead frame and the substrate. In the aforementioned conventional technique, it is expected to secure both of electrical connecting function and physical holding function in a joint portion of a main part only by soldering. Now, when such a joint portion is reviewed with respect to the lead frame for mounting high-performance semiconductor chip, it is usually related to QFP (Quad Flat Package) capable of having input and output multi-terminals. In such a QFP structure, the joint portion is formed in the outer periphery of four sides, but means for releasing stress based on the difference in thermal expansion between the lead frame and the substrate is not formed, so that such a stress is stored in the joint portion. As a result, when conducting, for example, a life test of a final product, breakage is caused in the joint portion and hence breakage is caused in respective wiring portion. PA1 [2] Since there is a state of completely connecting the lead frames to the conductor pattern of the substrate, the functions inherent to the substrate serving as internal wiring portion and semiconductor chip mounting portion are lost from the lead frame and hence the effective utility is obstructed and the degree of freedom in the design of the substrate is not sufficiently applied. PA1 [3] In the joining between the lead frame and the substrate, it is desirable to reduce the joint number as far as possible from viewpoints of increase of wiring resistance and degradation of joining reliability in the joint portion, but the reduction of the joint number to a desired number can not be attained. PA1 (1) Thermal stress is dispersed into the adhesive layer arranged on the outer periphery of the substrate and the electrical connecting portion to improve stress resistance; PA1 (2) Since a part of the lead frame is utilized as a printed wiring substrate, the connection to the respective semiconductor chip has a so-called tier type structure and hence the effective wiring density is increased. Furthermore, there are suppressed occurrences of wire crossing and short-circuit based on a resin flow in the molding; PA1 (3) The joint number in the device can surely be reduced in accordance with a given design for ground wire and various signal wires; and the like.